The present invention relates generally to a semiconductor device and a method for manufacturing the semiconductor device. More specifically, the invention relates to a semiconductor device which uses a stopper portion having a laminated structure of two kinds of materials or more in the chemical mechanical polishing (CMP) when forming a trench isolating region, and a method for manufacturing the semiconductor device.
Conventionally, the isolation of elements such as a MOS transistor has been carried out by forming a field insulator in, e.g., the local oxidation of silicon method (the LOCOS method). This performs isolation/diffusion and forms a field oxide film by the thermal oxidation using Si.sub.3 N.sub.4 covering a device portion as a mask.
Recently, in addition to this, a method for forming an insulating film by the trench isolation has been noticed. In the LOCOS method, a dimensional pattern shift is generated by bird's beaks. However, in this method, a delicate patterning can be achieved because such a bird's beak is not formed. This method has, e.g., the following advantages in comparison with the LOCOS method.
(1) There is little difference in level between an element forming region (a device portion) and an element isolating region (a field portion), so that the device is flat. PA0 (2) When patterning, a large margin of lithography can be ensured to obtain a large manufacturing margin, so that it is advantageous in a semiconductor process. PA0 (3) The insulating film is deeply buried, so that it is possible to isolate devices even in a delicate design.
FIGS. 11A through 11F schematically show steps in a conventional method for manufacturing a semiconductor device by the trench isolation.
The method for manufacturing a semiconductor device by the trench isolation includes a CMP step in which a stopper protecting an active layer in a polishing step is provided. Usually, this stopper is made of, e.g., a polycrystal silicon or a silicon nitride, and is formed so as to have a structure of only monolayer. Such a manufacturing method will be described below.
First, as shown in FIG. 11A, a semiconductor substrate 91 of silicon or the like and an oxide film 92 are formed. Then, a stopper 93 for use in the CMP is deposited thereon. The material of the stopper 93 may be, e.g., a polycrystal silicon, a silicon nitride (Si.sub.x N.sub.y) or the like. Thereafter, as shown in FIG. 11B, an element isolating region is patterned using the optical lithography or the like, and then, a trench is formed by, e.g., the anisotropic etching. As shown in FIG. 11C, the interior of the trench and so forth are oxidized to form an oxide film 94. Then, as shown in FIG. 11D, an insulating film 95 of, e.g., SiO.sub.2, is deposited on the whole surface of the substrate. Thereafter, as shown in FIG. 11E, the etchback and the flattening are simultaneously carried out by the CMP step. After the CMP is completed, the stopper 93 is peeled off by the isotropic etching to completely form an element isolating region as shown in FIG. 11F.
As shown in FIG. 11F, in the conventional method, the field end has a difference in level. In general, the stopper for use in the CMP step needs a certain thickness (for example, about several hundred nanometers). When the uniformity of the CMP is poor, the polishing depth may be different for every location of one wafer, i.e., for every element forming region. As a result, a great difference in level may occur at a certain location.